This invention relates to a digital-to-analog converter and, more particularly, to such a converter which is readily adapted to be constructed as an integrated circuit and may be formed of relatively low-cost resistive elements having a high range of tolerance without deleteriously affecting the resultant analog signal produced thereby.
A conventional digital-to-analog (D/A) converter typically is formed of a plurality of series-connected resistors coupled to a source of voltage potential so as to form a voltage divider network; and a particular tap of the voltage divider network is selected as a function of the digital signal which is to be converted to analog form. For example, a 3-bit digital signal may be converted to any one of eight possible analog levels. To convert such a 3-bit digital signal, eight series-connected resistors are coupled between a voltage source and, for example, ground. An analog output terminal is selectively connected by way of a so-called "switching tree" network to one of the seven taps which are formed by the 8-resistor string. Depending upon which tap is connected to the output terminal, the resultant analog output signal level will be equal to 1/8 V, 2/8 V, 3/8 V, . . . 6/8 V or 7/8 V, wherein V is the magnitude of the voltage source. In one type of switching tree network, the most significant bit of the 3-bit digital signal is used to select one or another path from the output terminal to the resistor string, depending upon whether the most significant bit is a binary "1" or "0". Similarly, in each path, the next most significant bit establishes one or another sub-path depending upon whether this next significant bit is a binary "1" or "0". Finally, each sub-path is connected to the resistor string through one or another switch depending upon whether the least significant bit is a binary "1" or "0".
When the aforementioned D/A converter is constructed as an integrated circuit, both the resistors and the switching tree are formed on the same chip or IC pellet. To consolidate space, the string of resistors may be disposed as comb-shaped resistors in a serpentine or zig-zag pattern. As one example, the resistors may be etched of photo-resist material. However, even with present-day integrated circuit technology, there is a strong likelihood that the resistance values of the resistors are not precisely equal. Typically, small errors are present in such resistance values, and these errors are cumulative from one end of the resistor string to the other. That is, if the ideal resistance value is R, the actual resistance value of the last resistor in the string may differ from R by a greater amount, or error, than the resistor at the beginning of the string.
In view of the foregoing, integrated circuit D/A converters generally are designed with resistors having resistance values that fall within a tolerable range of error. The maximum tolerable error is limited to that error which results in a change in the analog output level equal to one-half the voltage difference when the least significant bit of the digital signal changes over from one logic state to another. In a 3-bit D/A converter, the maximum tolerable error thus is equal to that change in resistance which results in an output analog voltage level change equal to 1/16 V.
In a 3-bit D/A converter having a string of eight resistors each of which having a resistance value that is within the tolerable error range discussed above, the overall resistance error of the eight resistors may be assumed to be equal to zero, with the first two resistors each having a resistance R-2.DELTA.r, the next two resistors each having a resistance R-.DELTA.r, the next two resistors each having a resistance R+.DELTA.r, and the last two resistors each having a resistance R+2.DELTA.r. This is consistent with the aforementioned integrated circuit fabrication wherein the resistance error generally may be viewed as increasing from the first to the last resistor in the string. Now, with such a D/A converter, if the digital signal to be converted is, for example, [100], the typical switching tree network connects the D/A converter output terminal to a generally center tap of the resistor string. The resultant voltage divider which is established thereby is constituted by the last four resistors of the string, thereby producing the output analog voltage level V.sub.out which is represented as: ##EQU1## As mentioned above, the maximum tolerable error is limited to .+-.1/16 V. Thus, the error due to the resistance error 6.DELTA.r/8R must be limited to 1/16, whereby the maximum tolerable resistance error .DELTA.r/R must be limited to .+-.8.3% for a 3-bit D/A converter. Using this analysis to calculate the maximum tolerable resistance error in an 8-bit D/A converter results in constructing resistors within a tolerance of .+-.0.4%. It is exceedingly difficult, and quite expensive, to manufacture integrated circuits having resistance values within .+-.0.4% limits.